A known data output driver serves to transfer a signal from the inside of a semiconductor element to the outside thereof. Compared with a P-type metal oxide semiconductor(PMOS) field effect transistor, an N-type metal oxide semiconductor (NMOS) field effect transistor needs a smaller layout area, and the mobility of its active carrier, that is, electron, is greater than that of the active carrier, that is, hole of the PMOS transistor. Therefore, data output drivers mostly utilizes NMOS transistors.
FIG. 1 illustrates a conventional data output driver. The data output driver has two NMOS transistors. A first NMOS transistor for pull-up has a gate receiving the data of data output buffer(not illustrated), and a drain connected to a power source voltage terminal. A second NMOS transistor 2 for pull-down has a gate receiving a reversed data of the data output buffer, and a source connected to a ground voltage terminal. A source of the first NMOS transistor 1 for output and a drain of second NMOS transistor 2 for output are commonly connected to an output node 3. The ground voltage terminal is connected to bulks of the first NMOS transistor 1 and the second NMOS transistor 2.
The operation of FIG. 1 will now be described. When the data having an ground voltage level V.sub.ss corresponding to low state is applied to the gate of the first transistor 1, the first NMOS transistor 1 turns off and the second NMOS transistor 2 turns on. Thereby the output of data output driver becomes logic "low" state. However, when the data having a power source level V.sub.cc corresponding to high state is applied to the gate of the first transistor 1, the NMOS transistor 1 turns on and the NMOS transistor 2 turns off. Thus the output of the data output driver becomes logic "high" state. Here, it is a well known fact in this field that the logic "low" state is usually lower than TTL (transistor-transistor logic)level, i.e., 0.8V and the logic "high" state is usually higher than TTL level, i.e., 2.4V. When logic "high" level is produced, the voltage of V.sub.CC -V.sub.TH is accumulated in the output node 3. Actually, however, a voltage difference between the voltage applied to the source of the first NMOS transistor 1 and the ground voltage applied to a bulk of the first NMOS transistor 1, makes voltage lower than the V.sub.CC -V.sub.TH level be accumulated in the output node 4. The reason is that a body effect causing the voltage difference between bulk and source produced when V.sub.SS is applied to the bulk of the first NMOS transistor and the first NMOS transistor turns on, raises the threshold voltage V.sub.TH to higher voltage itself.
In FIG. 2, a threshold voltage increased by body effect is illustrated. It shows that threshold voltage is increased by the voltage V.sub.BS (V.sub.SUBSTRATE --V.sub.SOURCE) due to the body effect.
The voltage V.sub.BS will be described briefly. When the voltage is applied to the source of NMOS transistor, a depletion layer adjacent to the source expands in proportional to the voltage applied to the source. Thus, only if the voltage corresponding to the expanded deletion layer, in addition to the threshold voltage itself, is applied to the gate of the NMOS transistor, a reverse layer between the drain and the source is formed, to turn on the NMOS transistor. In other words, a difference between the threshold voltage V.sub.TH formed before the expansion of the depletion layer of the source and the voltage V.sub.TH formed at the expansion of the depletion layer of the source, is V.sub.BS, and it is expressed in .alpha..
Accordingly, voltage of V.sub.CC --(V.sub.TH +.alpha.) is accumulated in the output node 3 of FIG. 1. This causes a decline in output gain(V.sub.OH). Particularly if the potential of power source voltage terminal is in logic "low" state, the output gain is lowered to considerably. Therefore, the conventional data output driver cannot sufficiently carry out the function of a data output driver requiring the high output gain.